Crafting a Chip, A Practical Guide to the UofU VLSI CAD Flow

Crafting a Chip, A Practical Guide to the UofU VLSI CAD Flow

Contains tutorials for powerful industrial strength EDA and CAD tools from Cadence and Synopsy, the same tools that major chip makers use to build commercial chips.

Publication date: 24 Aug 2006

ISBN-10: n/a

ISBN-13: n/a

Paperback: n/a

Views: 15,398

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Post time: 28 Jan 2007 08:01:52

Crafting a Chip, A Practical Guide to the UofU VLSI CAD Flow

Crafting a Chip, A Practical Guide to the UofU VLSI CAD Flow Contains tutorials for powerful industrial strength EDA and CAD tools from Cadence and Synopsy, the same tools that major chip makers use to build commercial chips.
Tag(s): Computer Organization and Architecture
Publication date: 24 Aug 2006
ISBN-10: n/a
ISBN-13: n/a
Paperback: n/a
Views: 15,398
Document Type: N/A
Publisher: n/a
License: n/a
Post time: 28 Jan 2007 08:01:52
Book Excerpts:

The design process for digital integrated circuits is extremely complex. Unfortunately, the Electronic Design Automation (EDA) and Computed Aided Design (CAD) tools that are essential to this design process are also extremely complex. Finding a combination of tools and a way of using those tools that works for a particular design is know as finding a "tool path" for that project. This book will introduce one path through these complex tools that can be used to design digital integrated circuits. The tool path described in this book uses tools from Cadence and Synopsys that are available to university students through special arrangements that these companies make with universities. Tool bundles that would normally cost hundreds of thousands or even millions of dollars if purchased directly from the companies are made available through "university programs" at small fixed fees.

In order to justify these small fees, however, the EDA companies typically reduce their costs by offering very limited support for these tools to university customers. In an industrial setting there would likely be an entire CAD support department whose job it is to get the tools running and to develop tool flows for projects within the company. Few universities, however, can afford that type of support for their CAD tools. That leaves universities to sink or swim with these complex tools making it all the more important to find a usable tool path through the confusing labyrinth of the tool suites. This book is an attempt to codify at least one working tool path for a Cadence/Synopsys flow that students and researchers can use to design digital integrated circuits. It includes tutorials for specific tools, and an extended example of how these tools are used together to design a simple integrated circuit.

In addition to the CAD tools from Cadence and Synopsys, The tutorials assume that the reader has some sort of CMOS standard cell library available. The specific examples in this book will use a cell library developed at the University of Utah specifically for our VLSI classes known as the UofU Digital library. This library, and the technology information available through the NCSU CDK (North Carolina State University Cadence Design Kit), are freely available from the University of Utah and North Carolina State University respectively. If the reader doesn’t have these libraries he should be able to follow most of the tutorials with his own library, but he must have a library of some sort.




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Erik Brunvand

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